Parallel replica CDR to correct offset and gain in a baud rate sampling phase detector
US9344272B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 26, 2015 |
| Grant date | May 17, 2016 |
| Priority date | — |
| Expiry date | Jan 26, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/042
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Apparatus and methods reduce channel-dependent phase detector offset and/or gain errors. A conventional Mueller-Muller phase detector places a main cursor at the midpoint of a pre-cursor and a post-cursor. However, for example, when the impulse response of an associated transmission line is not symmetric, the main cursor can be misaligned by conventional Mueller-Muller techniques. By providing a replica clock and data recovery path, trial and error experiments on the phase detector offset and/or gain can be performed, and relatively good values found for the phase detector offset and/or gain without disturbing the reception of data by the phase detector that is being used to receive data. These settings can then be used by the phase detector that is being used to receive data, which can improve the bit error rate of the phase detector.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.