Mask pattern alignment method and system
US9348240B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 27, 2012 |
| Grant date | May 24, 2016 |
| Priority date | — |
| Expiry date | Dec 10, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG03F9/7003
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
An alignment method includes dividing a wafer into a plurality of regions including a first region and a second region, and each region contains a plurality chip areas. The method also includes obtaining alignment offset values for the first region, and determining a first alignment compensation equation for the first region. The method also includes obtaining alignment offset values for the second region, and determining a second alignment compensation equation for the second region. Further, the method includes determining whether a chip area to be exposed is in the first region or the second region, when the chip area is in the first region, using the first alignment compensation equation to adjust alignment of the wafer and, when the chip area is in the second region, using the second alignment compensation equation to adjust the alignment of the wafer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.