Low power management of multiple sensor integrated chip architecture
US9348434B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 28, 2013 |
| Grant date | May 24, 2016 |
| Priority date | — |
| Expiry date | Jan 2, 2034 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/70
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method, device, system, or article of manufacture is provided for low-power management of multiple sensor chip architecture. In one embodiment, a method comprises, at a computing device that includes a first processor, a second processor and a third processor, receiving, by the first processor, sensor data from a first sensor; determining, by the first processor, a movement by the computing device using the sensor data; receiving, by the first processor, a modality of the computing device; in response to determining that the modality corresponds to a predetermined state, determining, by the first processor, a modality move distance associated with the predetermined state; determining, by the first processor, a move distance of the computing device using the modality move distance; determining, by the first processor, that the move distance of the computing device is at least a move distance threshold; and, in response to determining that the move distance of the computing device is at least a move distance threshold, reporting, by the first processor, to at least one of the second processor and the third processor, that the move distance of the computing device is at least the mo…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.