Patent · US Active

Memory centric computing

US9348539B1 · kind B1 · utility

25Cited by

1References

16Claims

0Family size

Assignee

INPHI CORPORATION · US

Inventors

Nirmal Saxena · Los Altos Hills, US
David T. Wang · Thousand Oaks, US
Christopher Haywood · Cary, US
Eric McDonald · Santa Clara, US
Chao Xu · Jiande, CN

Key dates

Filing date	Feb 28, 2014
Grant date	May 24, 2016
Priority date	—
Expiry date	Sep 18, 2034

Classification

Technology area (CPC G)Physics
CPC primaryG11C5/04
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A hybrid memory system. This system can include a processor coupled to a hybrid memory buffer (HMB) that is coupled to a plurality of DRAM and a plurality of Flash memory modules. The HMB module can include a Memory Storage Controller (MSC) module and a Near-Memory-Processing (NMP) module coupled by a SerDes (Serializer/Deserializer) interface. This system can utilize a hybrid (mixed-memory type) memory system architecture suitable for supporting low-latency DRAM devices and low-cost NAND flash devices within the same memory sub-system for an industry-standard computer system.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.