Run-time code parallelization with continuous monitoring of repetitive instruction sequences
US9348595B1 · kind B1 · utility
9Cited by
52References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Dec 22, 2014 |
| Grant date | May 24, 2016 |
| Priority date | — |
| Expiry date | Dec 22, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2201/865
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method includes, in a processor that executes instructions of program code, monitoring instructions of a repetitive sequence of the instructions that traverses a flow-control trace so as to construct a specification of register access by the monitored instructions. Based on the specification, multiple hardware threads are invoked to execute respective segments of the repetitive instruction sequence at least partially in parallel. Monitoring of the instructions continues in at least one of the segments during execution.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.