Method and system of synchronizing processors to the same computational point
US9348657B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 17, 2014 |
| Grant date | May 24, 2016 |
| Priority date | — |
| Expiry date | Sep 22, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/657
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system for synchronizing central processing units (CPU) includes a schedule module that communicates a synchronization point, a first CPU that writes a first memory address to a first register in response to the first CPU reaching the synchronization point, and a second CPU that writes a second memory address to a second register in response to the second CPU reaching the synchronization point. The system further includes a first logical AND module that writes a first value to a third register based on the first and second memory addresses and a second logical AND module that writes a second value to a fourth register based on the first and second memory addresses. The system also includes a scheduler module that selectively generates a processor sync signal based on the first and second value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.