Memory access controller, multi-core processor system, memory access control method, and computer product
US9348740B2 · kind B2 · utility
1Cited by
2References
5Claims
0Family size
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Key dates
| Filing date | Dec 6, 2012 |
| Grant date | May 24, 2016 |
| Priority date | — |
| Expiry date | Aug 18, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2209/522
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory access controller includes a semiconductor circuit configured to classify into a first group of cores having made an exclusive access request to shared memory and a second group of cores not having made an exclusive access request to the shared memory, multiple cores capable of accessing the shared memory; detect a core having completed the exclusive access among the first group of cores; and send to a core among the first group of cores and standing by for the exclusive access, a notification of release from a standby state, when detecting a core having completed the exclusive access.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.