Receiver and method for data processing
US9348776B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 22, 2013 |
| Grant date | May 24, 2016 |
| Priority date | — |
| Expiry date | Aug 15, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention discloses a receiver and a method for data processing. The receiver includes a system on chip and a memory, where the system on chip is connected to the memory through an external buffer bus; the system on chip includes an LLR subsystem, a controller, a rate matching module, an incremental redundancy IR reconstructing module, and a combiner, where the LLR subsystem is connected to the controller and the rate matching module respectively; the controller is connected to the IR reconstructing module, and the rate matching module and the IR reconstructing module are connected to the combiner respectively; and the controller stores LLR data currently corresponding to a data block demodulated by the LLR subsystem into a memory, and read LLR data historically corresponding to the data block and stored in the memory into the IR reconstructing module when the data block is a retransmitted data block.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.