Pixel circuit and display
US9349321B2 · kind B2 · utility
Assignees
Inventor
Key dates
| Filing date | Dec 12, 2013 |
| Grant date | May 24, 2016 |
| Priority date | — |
| Expiry date | Dec 12, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2320/0204
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A pixel circuit and a display are configured to reduce a size of the pixel circuit, so as to further reduce pixel pitch, increase the number of the pixels contained in per unit area and improve picture display quality. The pixel circuit includes: a first pixel sub-circuit and a second pixel sub-circuit, as well as an initialization module (31) and a data voltage writing module (32) connected to the first pixel sub-circuit and the second pixel sub-circuit; wherein the initialization module (31) is connected to a reset signal terminal and a low potential terminal, and is configured to initialize the first pixel sub-circuit and the second pixel sub-circuit under the control of a reset signal inputted from the reset signal terminal; the data voltage writing module (32) is connected to a data voltage terminal and a gate signal terminal, and is configured, under the control of a signal inputted from the gate signal terminal, to firstly write a first data voltage to the first pixel sub-circuit and the second pixel sub-circuit and perform compensation on a driving module (332) of the second pixel sub-circuit, and then to write a second data voltage to the first pixel sub-circuit and perfor…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.