Multi-layered chip electronic component
US9349512B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 2, 2012 |
| Grant date | May 24, 2016 |
| Priority date | — |
| Expiry date | Oct 2, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01F27/292
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
There is provided a multi-layered chip electronic component including: a multi-layered body including a 2016-sized or less and a plurality of magnetic layers; conductive patterns electrically connected in a stacking direction to form coil patterns, within the multi-layered body; and non-magnetic gap layers formed over a laminated surface of the multi-layered body between the multi-layered magnetic layers and having a thickness Tg in a range of 1 μm≦Tg≦7 μm, wherein the number of non-magnetic gap layers may have the number of gap layers in a range between at least four layers among the magnetic layers and a turns amount of the coil pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.