Method for mechanical stress enhancement in semiconductor devices
US9349655B2 · kind B2 · utility
2Cited by
3References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 24, 2009 |
| Grant date | May 24, 2016 |
| Priority date | — |
| Expiry date | Nov 18, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
Abstract
The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate having an active region; at least one operational device on the active region, wherein the operational device include a strained channel; and at least one first dummy gate disposed at a side of the operational device and on the active region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.