Semiconductor device
US9349719B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 11, 2014 |
| Grant date | May 24, 2016 |
| Priority date | — |
| Expiry date | Nov 11, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0174
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A semiconductor device is provided. The semiconductor device includes a first transistor on a first side of a shallow trench isolation (STI) region and a second transistor on a second side of the STI region. The first transistor includes a first conductive portion having a second conductivity type formed within a well having a first conductivity type, a first nanowire connected to the first conductive portion and a first active area, and a first gate surrounding the first nanowire. The second transistor includes a second conductive portion having the second conductivity type formed within the well, a second nanowire connected to the second conductive portion and a second active area, and a second gate surrounding the second nanowire. Excess current from an ESD event travels through the first conductive portion through the well to the second conductive portion bypassing the first nanowire and the second nanowire.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.