III-n device with dual gates and field plate
US9349805B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 29, 2014 |
| Grant date | May 24, 2016 |
| Priority date | — |
| Expiry date | Feb 12, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/343
Abstract
A semiconductor apparatus includes a substrate; a first semiconductor layer formed on the substrate and formed of a nitride semiconductor; a second semiconductor layer formed on the first semiconductor layer and formed of a nitride semiconductor; first and second gate electrodes, a source electrode, and a drain electrode formed on the second semiconductor layer; an interlayer insulation film formed on the second semiconductor layer; and a field plate formed on the interlayer insulation film. Further, the first gate electrode and the second gate electrode are formed between a region where the source electrode is formed and a region where the field plate is formed, an element isolation region is formed in the first and the second semiconductor layers which are between the first and the second gate electrodes, and the second gate electrode is electrically connected to the source electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.