Methods for fabricating a memory device with an enlarged space between neighboring bottom electrodes
US9349952B1 · kind B1 · utility
0Cited by
6References
12Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 8, 2014 |
| Grant date | May 24, 2016 |
| Priority date | — |
| Expiry date | Dec 8, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/823
Abstract
Embodiments of the present invention describe a method for fabricating a memory device comprising an enlarged space between neighboring bottom electrodes comprising depositing a poly-silicon layer on a substrate depositing a carbon layer above the poly-silicon layer, patterning a photo-resist layer on the carbon layer, depositing a first spacer layer on the photo-resist layer and performing a modified photolithography process on the photo resist layer after etching back the spacer layer creating sidewalls.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.