Patent · US Active

Reduced dynamic power D flip-flop

US9350325B2 · kind B2 · utility

1Cited by

5References

17Claims

0Family size

Assignee

QUALCOMM Incorporated · US

Inventors

Yanfei Cai · Shanghai, CN
Shuangqu Huang · Shanghai, CN
Qiang Dai · Suzhou, CN

Key dates

Filing date	May 30, 2012
Grant date	May 24, 2016
Priority date	—
Expiry date	May 30, 2032

Classification

Technology area (CPC H)Electricity
CPC primaryH03K3/356156
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

A CMOS D-type flip flop (D-FF) exhibits reduced power consumption by selectively disabling certain charging/discharging operations at specific circuit elements to minimize the capacitance of the circuit's internal nodes using a partial signaling technique. A clock inverter module may be used to provide a partial inverse clock signal that is the complement of a clock signal when a non-clock dependent input to the clock inverter module has a first value and to provide a fixed signal when the non-clock dependent signal has a second value. One or more MOSFETs controlled by the partial inverse clock signal do not charge or discharge when the non-clock dependent signal has the second value.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.