Phase-locked loop circuit having low close-in phase noise
US9350364B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 7, 2015 |
| Grant date | May 24, 2016 |
| Priority date | — |
| Expiry date | Apr 7, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/099
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Phase-locked loop (PLL) circuits and methods of operation are disclosed. At frequencies that are closer to a center frequency, the phase noise characteristics contributed by a crystal oscillator in a first PLL sub-circuit dominate over the phase noise characteristics contributed by a second PLL sub-circuit, resulting in low close-in phase noise in the overall PLL circuit output signal, while at frequencies farther from the center frequency, the phase noise characteristics contributed by the second PLL sub-circuit dominate over the phase noise characteristics contributed by the crystal oscillator in the first PLL sub-circuit, resulting in low phase noise in the overall PLL circuit output signal at those frequencies.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.