Apparatus for clock and data recovery
US9350572B1 · kind B1 · utility
Assignees
Inventors
Key dates
| Filing date | Nov 6, 2015 |
| Grant date | May 24, 2016 |
| Priority date | — |
| Expiry date | Nov 6, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/033
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An apparatus is provided. A first adder generates a first superposed signal in response to a first feedback equalization signal and an input signal. A second adder generates a second superposed signal in response to a second feedback equalization signal and the first superposed signal. An edge slicer generates an edge signal by slicing the first superposed signal. A data slicer generates a data signal by slicing the second superposed signal. An error slicer generates an error signal by slicing the second superposed signal. A CDR circuit generates a first and second clock signal in response to the data signal and the edge signal. An adaptive filter generates the reference signal and equalizer coefficients in response to data signal and the error signal. An equalizing unit generates the first feedback equalization signal and the second feedback equalization signal in response to the data signal and the equalizer coefficients.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.