Multi IQ-path synchronization
US9350589B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 21, 2014 |
| Grant date | May 24, 2016 |
| Priority date | — |
| Expiry date | Aug 21, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L27/2662
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Aspects of a wireless apparatus and a method for handling a modulated signal include a frequency generator that produces a clock signal, a first synchronization circuit that generates a first sync enable signal based on an even edge of the clock signal, a second synchronization circuit that generates a second sync enable signal based on an even edge of the clock signal, a first divider having a first initial operating condition that generates a first IQ path based on the first sync enable signal, and a second divider having a second initial operating condition that generates a second IQ path based on the second sync enable signal, wherein the first and second operating conditions are not equal when initially powered.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.