Systems, apparatuses, and methods for performing mask bit compression
US9354877B2 · kind B2 · utility
7Cited by
3References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Dec 23, 2011 |
| Grant date | May 31, 2016 |
| Priority date | — |
| Expiry date | Feb 16, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30181
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of systems, apparatuses, and methods for performing in a computer processor mask bit compression in response to a single mask bit compression instruction that includes a source writemask register operand, a destination writemask register operand, and an opcode are described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.