Memory system comprising nonvolatile memory device and method of adjusting read voltage based on sub-block level program and erase status
US9355724B2 · kind B2 · utility
12Cited by
6References
20Claims
0Family size
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Key dates
| Filing date | Nov 11, 2013 |
| Grant date | May 31, 2016 |
| Priority date | — |
| Expiry date | May 3, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of operating a nonvolatile memory device configured to erase a memory block in sub-block units comprises detecting state information of unselected sub-blocks associated with a selected sub-block comprising selected memory cells, adjusting a read bias of the selected memory cells based on the state information, and reading data from the selected memory cells according to the adjusted read bias. The state information indicates a number of the unselected sub-blocks having a programmed state or an erased state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.