Silicon shield for package stress sensitive devices
US9355968B2 · kind B2 · utility
2Cited by
4References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 26, 2014 |
| Grant date | May 31, 2016 |
| Priority date | — |
| Expiry date | Sep 26, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A surface mount semiconductor package, semiconductor device, and method for fabrication of the surface mount semiconductor package and electrical device are described that include a leadframe assembly, an integrated circuit device disposed on the leadframe assembly, a silicon shield disposed on the integrated circuit device, where the silicon shield is configured to mitigate packaging stress to the integrated circuit device, and a molding layer that encapsulates the integrated circuit device, the silicon shield, and at least a portion of the leadframe assembly.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.