Chip package and method for forming the same
US9355975B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 23, 2014 |
| Grant date | May 31, 2016 |
| Priority date | — |
| Expiry date | Jul 23, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3701
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A chip package including a chip having an upper surface, a lower surface and a sidewall is provided. The chip includes a signal pad region adjacent to the upper surface. A first recess extends from the upper surface toward the lower surface along the sidewall. At least one second recess extends from a first bottom of the first recess toward the lower surface. The first and second recesses further laterally extend along a side of the upper surface, and a length of the first recess extending along the side is greater than that of the second recess extending along the side. A redistribution layer is electrically connected to the signal pad region and extends into the second recess. A method for forming the chip package is also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.