Three-dimensional chip stack and method of forming the same
US9355980B2 · kind B2 · utility
16Cited by
2References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 3, 2013 |
| Grant date | May 31, 2016 |
| Priority date | — |
| Expiry date | Dec 15, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/13091
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A three-dimensional chip stack includes a first chip bonded to a second chip to form a bonded interconnection therebetween. The bonded interconnection includes a first conductive pillar overlying a first substrate of the first chip, a second conductive pillar overlying a second substrate of the second chip, and a joint structure between the first conductive pillar and the second conductive pillar. The joint structure includes a first IMC region adjacent to the first conductive pillar, a second IMC region adjacent to the second conductive pillar, and a metallization layer between the first IMC region and the second IMC region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.