Thin film transistor array substrate and driving method therefor as well as liquid crystal display
US9356053B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Dec 3, 2012 |
| Grant date | May 31, 2016 |
| Priority date | — |
| Expiry date | May 7, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2340/0435
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A thin film transistor array substrate, a driving method therefore, and a liquid crystal display are disclosed. The thin film transistor array substrate includes at least a sub-pixel region formed by a gate line and a data line intersected with each other, wherein, each sub-pixel comprises a first transistor (21) of which the gate is connected with a gate line and the drain is connected with a data line and a first storage capacitor (23) of which one end is connected with the source of the first transistor (21) and the other end is connected with an output of a reference voltage, the sub-pixel further comprises a second storage capacitor (24) and a second transistor (25), wherein one end of the second storage capacitor (24) is connected with the source of the first transistor (21), and the other end of the second storage capacitor (24) is connected with the drain of the second transistor (25); the source of the second transistor (25) is connected with the output of the reference voltage, and the gate of the second transistor (25) is connected with an output of an Enable signal. Since a second storage capacitor (24) is additionally added to each sub-pixel in the thin film transistor…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.