Methods of forming patterns and methods of manufacturing semiconductor devices using the same
US9356071B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 20, 2015 |
| Grant date | May 31, 2016 |
| Priority date | — |
| Expiry date | Jul 20, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N50/80
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An insulation layer is formed on a substrate. A first mask is formed on the insulation layer. The first mask includes a plurality of line patterns arranged in a second direction. The plurality of line patterns extend in a first direction substantially perpendicular to the second direction. A second mask is formed on the insulation layer and the first mask. The second mask includes an opening partially exposing the plurality of line patterns. The opening has an uneven boundary at one of a first end portion in the first direction and a second end portion in a third direction substantially opposite to the first direction. The insulation layer is partially removed using the first mask and the second mask as an etching mask, thereby forming a plurality of first trenches and second trenches. The plurality of first trenches and the second trenches are arranged in a staggered pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.