Method of producing a junction field-effect transistor (JFET)

US9356113B2 · kind B2 · utility

Assignees

• INSTITUT NATIONAL DES SCIENCES APPLIQUÉES DE LYON · FR
• UNIVERSITE CLAUDE BERNAD LYON 1 · FR
• CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE · FR
• ECOLE CENTRALE DE LYON · FR
• Consejo Superior De Investigaciones Cienti{acute over (f)}icas (CSIC) · ES

Inventors

• Dominique Tournier · Val-de-Reuil, FR
• Florian Chevalier · Orange, FR
• Philippe Godignon · Sant Cugat del Vallès, ES
• Jose Luis Millan · San Diego, US

Key dates

• Filing date: Sep 5, 2012
• Grant date: May 31, 2016
• Expiry date: Sep 5, 2032

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/8503
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

The invention concerns a method for producing a field effect transistor having a trench gate comprising: —the forming (110) of at least one trench (11, 12, 13) in a semi-conductive substrate (1) having a first type of conductivity, said substrate comprising two opposing faces called front face and rear face, —the primary implantation (120) of ions having a second type of conductivity so as to implant each trench of the substrate to form an active gate area, —the depositing (160) of a layer of polycrystalline silicon having the second type of conductivity on the implanted active gate area, —the oxidation (160) of the layer of polycrystalline silicon, and —the metallization (180) of the substrate on the front and rear faces of same in order to form active source and drain areas.