Method for fabricating multi-gate structure device with source and drain having quasi-SOI structure
US9356124B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 30, 2013 |
| Grant date | May 31, 2016 |
| Priority date | — |
| Expiry date | Sep 30, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/667
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating a multi-gate structure device with a source and a drain having a quasi-SOI structure, comprising forming an active region in a shape of a fin bar, forming an oxide isolation layer for shallow trench isolation (STI), forming a polysilicon dummy gate, forming source and drain extension regions, forming the source and the drain with the quasi-SOI structure, and forming a high-K metal gate. Solution(s) consistent with the present innovations may be achieved by using a process method compatible with the conventional bulk silicon CMOS processes and can be easily integrated into the process flow. Moreover, innovations here may provide a small leakage current even in a case of having a short channel length, thereby reducing the power consumption of the device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.