Engineered source/drain region for n-Type MOSFET
US9356136B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 7, 2013 |
| Grant date | May 31, 2016 |
| Priority date | — |
| Expiry date | Apr 19, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/017
Abstract
Integrated circuit devices with field effect transistors have source and drain regions that include a first and a second layer. The first layer is formed below the plane of the channel region. The first layer includes doped silicon and carbon that has a crystal lattice structure that is smaller than that of silicon. The second layer is formed over the first layer and rises above the plane of the channel region. The second layer is formed by a material that includes doped epitaxially grown silicon. The second layer has an atomic fraction of carbon less than half that of the first layer. The first layer is formed to a depth at least 10 nm below the surface of the channel region. This structure facilitates the formation of source and drain extension areas that form very shallow junctions. The devices provide sources and drains that have low resistance while being comparatively resistant to short channel effects.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.