High speed, rail-to-rail CMOS differential input stage
US9356570B2 · kind B2 · utility
2Cited by
4References
5Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 28, 2014 |
| Grant date | May 31, 2016 |
| Priority date | — |
| Expiry date | Jul 28, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/45116
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An apparatus is provided, comprising a single-ended input stage with signals IN_P & IN_N as input and OUT_P & OUT_N as output, wherein the differential input controlled by transistors P1-3 and N1-N3; and a means for weighting (sizing) of transistor (P1 & P3) relative to P2 and (N1 & N3) relative to N2 defines the optimal operation mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.