Method and apparatus to calibrate frequency synthesizer
US9356612B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 13, 2014 |
| Grant date | May 31, 2016 |
| Priority date | — |
| Expiry date | Nov 13, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/197
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Aspects of the disclosure provide a circuit that includes a detector, a loop filter and a controller. The detector is configured to generate a first signal indicative a timing difference between a reference clock signal and a feedback clock signal. The feedback clock signal is generated based on an oscillating signal from an oscillator. The oscillator includes a first tuning circuit and a second tuning circuit to tune a frequency of the oscillating signal. The loop filter is configured to filter out a portion of frequency components from the first signal to generate a second signal for tuning the first tuning circuit of the oscillator. The controller is configured to tune the second tuning circuit based on the first signal and the second signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.