Systems and methods for comparator calibration
US9356615B1 · kind B1 · utility
13Cited by
5References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 6, 2015 |
| Grant date | May 31, 2016 |
| Priority date | — |
| Expiry date | Nov 6, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/662
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present invention is directed integrated circuits and methods thereof. More specifically, an embodiment of the present invention provides a comparator calibration loop where a digital integrator stores a running sum based on the output of a comparator. A DAC converts the running sum and generates an offset calibration voltage, which is filtered by a low-pass filter module, and the filtered offset calibration voltage is used to cancel out the intrinsic offset voltage and low frequency noise of the comparator. There are other embodiments as well.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.