Pipelined interpolating sub-ranging SAR analog-to-digital converter
US9356616B1 · kind B1 · utility
3Cited by
2References
20Claims
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Key dates
| Filing date | Aug 3, 2015 |
| Grant date | May 31, 2016 |
| Priority date | — |
| Expiry date | Aug 3, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/46
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A multi-bit per cycle successive approximation register (SAR) analog-to-digital converter (ADC) may sample an input signal, successively approximate the sampled signal with a shrinking sub-range containing the signal, and output coarse digital codes corresponding to the sub-range. A sub-ranging stage may continue quantization over the sub-range by sampling and interpolating between a pair of zero crossing signals that bound the sub-range. The zero crossing signals may be taken from the SAR preamp output. The sub-ranging process may be pipelined recursively in multiple stages to increase throughput and efficiency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.