Methods and systems for chip-to-chip communication with reduced simultaneous switching noise
US9357036B2 · kind B2 · utility
1Cited by
96References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 1, 2015 |
| Grant date | May 31, 2016 |
| Priority date | — |
| Expiry date | Sep 1, 2035 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Systems and methods are described for transmitting data over physical channels to provide a high speed, low latency interface such as between a memory controller and memory devices with significantly reduced or eliminated Simultaneous Switching Output noise. Controller-side and memory-side embodiments of such channel interfaces are disclosed which do not require additional pin count or data transfer cycles, have low power utilization, and introduce minimal additional latency. In some embodiments of the invention, three or more voltage levels are used for signaling.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.