Reduced power mode of a cache unit
US9360924B2 · kind B2 · utility
2Cited by
0References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 29, 2013 |
| Grant date | Jun 7, 2016 |
| Priority date | — |
| Expiry date | Mar 30, 2034 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In an embodiment, a processor includes a plurality of cores and a cache unit reserved for a first core of the plurality of cores. The cache unit may include a first cache slice, a second cache slice, and power logic to switch operation of the cache unit between a first operating mode and a second operating mode. The first operating mode may include use of both the first cache slice and the second cache slice. The second operating mode may include use of the first cache slice and disabling the second cache slice. Other embodiments are described and claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.