SMS4 acceleration processors, methods, systems, and instructions
US9361106B2 · kind B2 · utility
11Cited by
2References
23Claims
0Family size
Assignee
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Key dates
| Filing date | Dec 27, 2013 |
| Grant date | Jun 7, 2016 |
| Priority date | — |
| Expiry date | Feb 27, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2209/125
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor of an aspect includes a plurality of packed data registers and a decode unit to decode an instruction. The instruction is to indicate one or more source packed data operands. The one or more source packed data operands are to have four 32-bit results of four prior SMS4 rounds. The one or more source operands are also to have a 32-bit value. An execution unit is coupled with the decode unit and the plurality of the packed data registers. The execution unit, in response to the instruction, is to store a 32-bit result of a current SMS4 round in a destination storage location that is to be indicated by the instruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.