Tag-based implementations enabling high speed data capture and transparent pre-fetch from a NOR flash
US9361117B2 · kind B2 · utility
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Key dates
| Filing date | Apr 30, 2014 |
| Grant date | Jun 7, 2016 |
| Priority date | — |
| Expiry date | Feb 24, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments disclosed herein generally relate for efficiently retrieving boot code for a processor from serial NOR flash memory. When a boot code request is received, a request handler in data capture logic tags successive address read requests to indicate whether the requests indicate contiguous addresses in the NOR flash memory for the boot code. Different circuitry in the data capture logic operates on different mesochronous clock signals. One clock signal drives the capture of boot code from NOR flash, and the other controls synchronized tagging, storing, pre-fetching, and transmitting of the captured boot code data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.