Pseudo-random error insertion for network testing
US9361197B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 30, 2014 |
| Grant date | Jun 7, 2016 |
| Priority date | — |
| Expiry date | Dec 13, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L69/00
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A method is provided for generating errored test message words in network traffic used for testing. The method includes for each error cycle, select an error generator threshold, using a pseudo random sequence generator that advances with a new error cycle. The method includes for each test word generation cycle, determine whether to apply a bit error mask to a generated test word. An accumulator value is accumulated by an increment that takes into account at least a bit error rate and a bus width. The accumulator value is tested against the threshold. Upon reaching the threshold, a bit error mask is selected from a set of bit error masks, and applied to the generated test word. The threshold is then subtracted from the accumulator value, and a new error generator threshold is selected. The generated test word is output with or without a bit error as determined.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.