Patent · US Active

Computation apparatus with coordination of the access to an internal memory and operating method

US9361212B2 · kind B2 · utility

1Cited by
1References
7Claims
0Family size

Assignee

Inventors

Key dates

Filing dateJun 10, 2010
Grant dateJun 7, 2016
Priority date
Expiry dateDec 24, 2031

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG06F9/54
  • WIPO fieldComputer technology
  • WIPO sectorElectrical engineering

Abstract

A programmable logic controller (PLC) with changing memory access times is intended to interact with a subordinate system, i.e., a discontinuous virtualized system, wherein a computation apparatus is provided, in which the PLC is implemented and in which the system that is subordinate to the PLC with respect to an operation to access the memory access is implemented. A memory to which a component of the PLC has access is integrated in the PLC. Also implemented in the computation apparatus is a proxy device that coordinates access to the memory of the PLC by the subordinate system such that simultaneous access by the component of the PLC has priority over access by the subordinate system and it is thus possible to ensure that the PLC always complies with a predefined cycle time of the PLC.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.