Constrained placement of connected elements
US9361419B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 6, 2014 |
| Grant date | Jun 7, 2016 |
| Priority date | — |
| Expiry date | Aug 6, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An improved method for the placement and routing of compound elements, each comprising a series/parallel combination of nominally identical elements, is disclosed. The method treats each compound element as a separate cell (the sub-circuit construct commonly used in silicon chip design) so as to treat as a unit all the nominally identical elements that make up a compound value, and place them as a single group in the design of a chip. This results in the compound elements being placed as units and routed in such a way that all of the nominal elements are located together and any effects between compound values are thus relatively localized and optimally isolated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.