Graphic processing circuit with binning rendering and pre-depth processing method thereof
US9361697B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 23, 2014 |
| Grant date | Jun 7, 2016 |
| Priority date | — |
| Expiry date | Dec 23, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T15/40
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A graphic processing circuit with binning rendering and associated pre-depth processing method is provided. Firstly, a first depth data of a first primitive corresponding to a specified tile is received. Then, the pre-depth data corresponding to the specified tile is read from a pre-Z buffer. If the first depth data is not larger than the pre-depth data and the first primitive is an opaque primitive, the pre-depth data is updated with the first depth data. If the first depth data is not larger than the pre-depth data and the first primitive is a translucent primitive, an uncertainty ordering range is defined according to the first depth data and the pre-depth data, and the pre-depth data is updated with the uncertainty ordering range.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.