Patent · US Active

Configuration for power reduction in DRAM

US9361970B2 · kind B2 · utility

1Cited by

2References

11Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Andre Schaefer · Hersbruck, DE
John B. Halbert · Beaverton, US

Key dates

Filing date	Jul 9, 2014
Grant date	Jun 7, 2016
Priority date	—
Expiry date	Jul 9, 2034

Classification

Technology area (CPC Y)Emerging Cross-Sectional Technologies
CPC primaryY02D10/00
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Disclosed embodiments may include an apparatus having a segment wordline enable coupled to logic to selectively disable ones of a number of segment wordline drivers. The logic may partition a page of the apparatus to reduce power consumed through activation of the disabled ones of the number of segment wordlines. Other embodiments may be disclosed.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.