Series connected resistance change memory device
US9361978B2 · kind B2 · utility
1Cited by
2References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 20, 2012 |
| Grant date | Jun 7, 2016 |
| Priority date | — |
| Expiry date | Sep 20, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/8828
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention is provided to suppress a current supplied to a storage element so as not to vary for each layer in a semiconductor memory device obtained by connecting a plurality of memory cells in series.A semiconductor memory device according to the invention includes a plurality of memory cells connected in series between a first signal line and a second signal line, and supplies a different gate voltage to at least two of selection transistors included in the memory cells, respectively (refer to FIG. 2).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.