Nonvolatile memory devices including simultaneous impedance calibration and input command
US9361985B2 · kind B2 · utility
7Cited by
13References
13Claims
0Family size
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Key dates
| Filing date | Dec 31, 2013 |
| Grant date | Jun 7, 2016 |
| Priority date | — |
| Expiry date | Mar 7, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2254
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An operating method of a nonvolatile memory device is provided which includes receiving a command sequence; detecting whether the input command sequence accompanies an impedance calibration operation; and if the input command sequence accompanies the impedance calibration operation, simultaneously performing an operation corresponding to the input command sequence and the impedance calibration operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.