Method for tuning threshold voltage of semiconductor device with metal gate structure
US9362385B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 18, 2013 |
| Grant date | Jun 7, 2016 |
| Priority date | — |
| Expiry date | Dec 18, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/121
Abstract
A method for manufacturing a metal gate structure includes forming a high-k dielectric layer in a gate trench; forming an etch stop over the high-k dielectric layer; forming a work function adjusting layer over the etch stop by forming a tri-layer by an atomic layer deposition (ALD) operation with a sequence of a grain boundary engineering layer configured to allow a dopant atom to penetrate there through, a doping layer configured to provide the dopant atom to the grain boundary engineering layer, and a capping layer configured to prevent the doping layer from oxidation; and filling metal to level up the gate trench. The grain boundary engineering layer is prepared by the ALD operation under various temperatures such as from about 200 to about 350 degrees Celsius.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.