Patent · US Active

On-chip vertical three dimensional microstrip line with characteristic impedance tuning technique and design structures

US9362606B2 · kind B2 · utility

2Cited by

23References

20Claims

0Family size

Assignees

International Business Machines Corporation · US
UNIVERSITY OF SOUTH CAROLINA · US

Inventors

Barbara S. DeWitt · South Burlington, US
Essam Mina · South Burlington, US
B M Farid Rahman · West Columbia, US
Guoan Wang · South Burlington, US

Key dates

Filing date	Aug 23, 2013
Grant date	Jun 7, 2016
Priority date	—
Expiry date	Oct 4, 2033

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/0002
WIPO fieldTelecommunications
WIPO sectorElectrical engineering

Abstract

A vertical three dimensional (3D) microstrip line structure for improved tunable characteristic impedance, methods of manufacturing the same and design structures are provided. More specifically, a method is provided that includes forming a first microstrip line structure within a back end of the line (BEOL) stack. The method further includes forming a second microstrip line structure separated from the BEOL stack by a predetermined horizontal distance.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.