System and method for analog to digital conversion
US9362935B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 13, 2013 |
| Grant date | Jun 7, 2016 |
| Priority date | — |
| Expiry date | Aug 13, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/361
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Parallel analog to digital converted (ADC) architectures that can be used to replace single path ADC architectures. The parallel ADC architecture can comprise N branches and one ADC per branch. These ADCs can be identical. However each branch can have a different path adjustments applied to the ADC. The path adjustments can be biases and/or gains and each ADC receives a different combination of biases and/or gain to generate multiple adjusted input signals. These are then combined to generate a quantized output signal. Using these parallel architectures a range of weighting and offset combining schemes can be employed to achieve improvements in signal to noise ratio and to reduce the impact of clipping as compared to a single path ADC architecture.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.