Circuit to recover a clock signal from multiple wire data signals that changes state every state cycle and is immune to data inter-lane skew as well as data state transition glitches
US9363071B2 · kind B2 · utility
7Cited by
43References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 6, 2014 |
| Grant date | Jun 7, 2016 |
| Priority date | — |
| Expiry date | Mar 6, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/493
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A clock recovery circuit is provided comprising a receiver circuit and a clock extraction circuit. The receiver circuit may be adapted to decode a differentially encoded signal on a plurality of data lines, where at least one data symbol is differentially encoded in state transitions of the differentially encoded signal. The clock extraction circuit may be adapted to obtain a clock signal from state transition signals derived from the state transitions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.