Clock-embedded vector signaling codes
US9363114B2 · kind B2 · utility
99Cited by
94References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 2, 2015 |
| Grant date | Jun 7, 2016 |
| Priority date | — |
| Expiry date | Mar 2, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/085
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Vector signaling codes providing guaranteed numbers of transitions per unit transmission interval are described, along with methods and systems for their generation and use. The described architecture may include multiple communications sub-systems, each having its own communications wire group or sub-channel, clock-embedded signaling code, pre- and post-processing stages to guarantee the desired code transition density, and global encoding and decoding stages to first distribute data elements among the sub-systems, and then to reconstitute the received data from its received sub-system elements.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.