Semiconductor display device comprising an upper and lower insulator arranged in a non-display area
US9366933B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 13, 2013 |
| Grant date | Jun 14, 2016 |
| Priority date | — |
| Expiry date | Sep 13, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG02F1/136227
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
An array board (a semiconductor device) 11b includes a display area TFT (a display area transistor) 17, a non-display area TFT (a non-display area transistor) 29, an upper insulator 31, and a lower insulator 30. The display area TFT 17 is arranged in a display area AA. The non-display area TFT 29 is arranged in a non-display area NAA. The upper insulator 31 is arranged in the non-display area NAA and formed from a second interlayer insulation film 41. The lower insulator 30 is arranged in the non-display area and formed from a first interlayer insulation film 39. The lower insulator 30 is arranged below the upper insulator 31 such that they are layered.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.