Apparatus to reduce idle link power in a platform

US9367116B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Paul S. Diefenbaugh · Portland, US
• Robert E. Gough · Cornelius, US
• Yuval Bachrach · Haifa, IL
• Mikal C. Hunsaker · Cameron Park, US
• Rafi Ben-Tal · Yoqneam Illit, IL
• Ilan Pardo · Ramat HaSharon, IL
• Gideon Prat · Haifa, IL
• David J. Harriman · Sacramento, US

Key dates

• Filing date: Dec 22, 2015
• Grant date: Jun 14, 2016
• Expiry date: Dec 22, 2035

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y02D10/00
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A system on a chip (SoC) is provided including processing cores and a root complex. The transaction requests are communicated between a root port of the root complex and a device, the root port including electrical idle (EI) exit detect circuitry and a reference clock source. The root port supports a first link state, in which the reference clock source and EI exit detect circuitry of the root port are disabled but a common mode voltage is maintained, and a second link state, in which the reference clock source and EI exit detect circuitry are disabled and the common mode voltage is not maintained. The root port transitions to the first link state based on a service latency requirement of the device being less than a threshold and to the second link state based on the service latency requirement being greater than or equal to the threshold.